Moslogi is looking for some expert RTL Front End Design Engineers, having good knowledge of ASIC design flow. This will be a very challenging and exciting role and will involve very complex designs.

Job Responsibilities

• Chip integration of high complexity SOCs.
• Coordinating with various IP owners on receivables and DV, synthesis and Emulation for deliverables
• Spyglass/CDC for the full chip and will evaluate the incoming bugs and take appropriate action
• Formal Verification between RTL to Netlist and Netlist to Netlist
• Manual and Conformal ECO
• Running Lint (Spyglass) at SoC level.
• Chip level integration and connectivity.
• Debugging FV failures
• ECO implementation.

Desired Skills and Experience

• 3+ years of experience
• Sound knowledge in Micro Architecture design and RTL implementation
• Understanding of ARM SoCs with AXI/AHB buses, peripherals, CPUs and mobile SOCs is desirable
• Experience in Synthesis and pre-layout timing analysis
• Understanding of DFT flow is desirable
• Experiencing using clear case a must
• Experienced with VHDL/Verilog/coding and tools like VCS/Verdi/Spyglass/Mentor Zero-in
• Proficiency in LEC and formal flows.
• Experience in Perl, TCL and shell scripting
• Excellent interpersonal & analytical skills with ability to work independently

Moslogi is looking for smart and enterprising Physical Designer Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Always Fun and Exciting. This role will involve Physical design at block and chip level of complex designs in the latest technologies.

Desired Skills and Experience

• 3+ years relevant experience
• Excellent hands on P&R skills with expert knowledge in ICC / Innovus
• Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background of Floor planning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing and Signal Integrity closure
• Experience at taping out multiple chips, strong experience at top level at latest technology nodes

Moslogi is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution

This role will include

• Lead an internal IP Verification team, executing projects for an offshore client
• Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects
• Guide team members in verifying IP’s and delivering zero bug IP’s
• Manage the team and their technical and leadership growth
• Manage all interactions with the client

Desired Skills and Experience

• 3+years experience in Design Verification
• Expert Knowledge in IP Verification
• Very strong knowledge in multiple protocols is highly desired, AMBA protocols and at least one high speed interface
• Must have expert knowledge in coverage driven test planning
• Must have expert knowledge in architecting configurable environments
• Must have very strong System Verilog and UVM background
• Must be able to lead the team technically in all aspects, must be able to drive multiple projects
• Past experience leading and managing teams highly desired
• Excellent Communication and Presentation Skills
• Ability and desire to learn new methodologies, languages, protocols etc. is required

Moslogi is looking for some expert Analog Layout Engineer, having good knowledge of Analog IC Layout design.

Experience: 3+ years of experience as Analog Layout Engineer Key Skills:

Desired Skills and Experience

• Analog IC Layout
• DRC/LVS/Antenna/LPE checks
• CMOS/BiCMOS device physics
• CMOS/BiCMOS fabrication knowledge
• Perl and Shell scripting(prefer)

Responsibilities

• Work on custom layout Analog IPs like PLL, ADCs, DACs, Voltage Reference Generators, High speed IOs and custom layout of standard cells
• Hands on experience in Full chip layout, (other mixed signal or RF layout would be plus)
• Performing verification checks like DRC/LVS/Antenna and fixing violations
• Work closely with the design engineers and layout engineers in designing and successfully delivering Analog Layouts
• Need to work and review layouts which produces good yield
• Experience in using Cadence Virtuoso Layout Editor, Mentor Graphics Calibre verification tool (Assura and/or Hercules is plus)
• Performing various kinds of Analog Layouts, implementations from top-level floor planning down to complex block level layouts
• Knowledge of various Analog Layout Techniques
• Understanding of circuit principles as affected by layout such as speed, capacitance, power, noise and area
• Ability to exchange and communicate information with Analog Designers and the team members
• Possess good team building skills
• Excellent communication, documentation and presentation skills

Moslogi is looking for engineers well versed with placement aware Synthesis, power aware synthesis, constraints validation, STA & Formal Validation.

Desired Skills and Experience

• 3+ Years in Synthesis / STA engineer
• Complete understanding of Syn/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF) and various flow
• Develop/Plan complete DFT/test strategy for the device as per SOW
• Create DFT implementation plan, delegate to team members and tracking
• Test mode timing support/debug and closure at full chip level
• Handle post-silicon pattern generation, Validation and ATE debug/support
• Understanding Test/DFT modes SDC
• Complete familiarity of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan) with expertise in one of them
• Independently handle IP verification strategy and implement and verify the same
• Good exposure to STA tool. Assist STA team in timing closure for DFT modes
• Good scripting skills (TCL/Perl)
• Familiarity with PD concepts/flow and assist PD team if and when required

Moslogi  is looking for expert DFT engineers for development, support, maintenance, Implementation and Testing of complex components of an ASIC/SOC/FPGA/Board.

Job Location

Bangalore, India

Desired Skills and Experience

• 3 year’s experience in DFT
• DFT architecture definition w.r.t. test time/cost, coverage, test power. Good experience/concept on all aspect of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.
• DFT logic integration and verification.
• Experience on debugging low coverage.
• Gate Level DFT verification with and without timing.
• Pattern generation, verification and delivery to ATE team.
• Post silicon debug and support on failing patterns.
• Experience of leading small DFT team is plus.
• Good experience on EDA tools of reputed vendor like Mentor, Synopsis. LBIST experience is plus.
• DFT mode STA and timing closer support.

• Exp. Level- 3-6 Yrs
• Qualification: BE/B.Tech/ME/M.Tech Only

Desired Skills and Experience

• At least 3 years AUTOSAR RTE relevant working experience
• Be familiar with AUTOSAR development procedure
• Be familiar with AUTOSAR toolchain
• Experience in Configuration and Integration of MCAL and OS with application
• Familiar with CANalyser, CANoe, Safety Standards(ISO 26262), CAN /FlexRay Protocol, Vehicle Architecture, Diagnostics
• Strong debugging skills and use of debugger such as Lauterbach
• Experience in developing embedded software in ‘C’ is required